Public Preview Zyphar model now available — sign up and generate

Introducing Zyphar, the first generative model for physical chip design.

An end-to-end generative engine for VLSI physical design. Accelerate your tapeout from weeks to days with high-fidelity GDSII generation.

Backed by
Inception Program
Google Research Program
ASCII-art rendering of a chip layout generated by Zyphar

Zyphar

A foundational generative model, purpose-built for the physical design of chips.

Zyphar assists VLSI engineers through every stage of physical design, from floorplanning and placement to routing and GDSII generation. This release is a public preview of the model and is not the proprietary production system; capabilities, interfaces, and outputs may change as we continue training and evaluation.

[01] End-to-end GDSII generation
[02] DRC and LVS-aware inference
[03] Multi-foundry PDK support

Start generating with Zyphar.

Create a free account and submit your first netlist in minutes. For enterprise PDK access, tapeout support, or custom deployments, reach out.

Location San Francisco, CA
Stage Public preview