An end-to-end generative engine for VLSI physical design. Accelerate your tapeout from weeks to days with high-fidelity GDSII generation.
A foundational generative model, purpose-built for the physical design of chips.
Zyphar assists VLSI engineers through every stage of physical design, from floorplanning and placement to routing and GDSII generation. This release is a public preview of the model and is not the proprietary production system; capabilities, interfaces, and outputs may change as we continue training and evaluation.
Zyphar is in private beta for semiconductor teams taping out on commercial PDKs. Tell us about your design flow and we will get back within 48 hours.
